1. Field of the Invention
The present invention relates to semiconductor integrated circuits and in particular to a circuit that compensates the phase of a periodic input signal such as a clock signal.
2. Description of the Related Art
A phase compensation circuit for clock signal is widely used in a memory and a processor etc. to compensate the phase of a reference signal and the phase of a feedback signal.
FIG. 10 is a drawing showing an example of the structure of a conventional phase compensation circuit. Referring to FIG. 10, this conventional phase compensation circuit is structured to provide a first variable delay circuit 1, in which the delay time between an input signal 100 and output signal 101 can be variably set, a first phase comparator 5 that compares the phase of a reference signal 102 and the phase of a feedback signal 103, which is the fed back output of the first variable delay circuit 1, and a control circuit 4.
The result of the comparison of the phases of the reference signal 102 and the feedback signal 103 in the first phase comparator 5 is supplied to the control circuit 4, and in the control circuit 4, based on the results of this comparison, the setting and control of the delay time of the first variable delay circuit 1 are carried out so that the phase of the reference signal 102 is the same as the phase of the feedback signal 103.
FIG. 11 is a drawing showing the relationship between the delay adjusted value of the first variable delay circuit 1 and the delay time. And shown in FIG. 11, the phase of the output of the first variable delay circuit 1 can be controlled within a variable delay time range.
Moreover, as a totally digital phase adjustment method providing a digitally adjustable delay circuit, Japanese Patent Application, First Publication, Hei 6-303096, proposes a phase shift method in which an infinitely long delay line is simulated by identifying a continuous terminal at a physical position along the delay line. In addition, Japanese Patent Application, First Publication, Hei 11-88153, discloses for example a digital DLL (delay locked loop) circuit providing a variable delay circuit that delays an input signal, a phase comparator that compares the phases of a reference signal and a feedback signal, and a counter that decrements the count value based on the output of the phase comparator and thereby controls the delay time of the variable delay circuit. Furthermore, in Japanese Patent Application, First Publication, Hei 11-55091, discloses a variable delay circuit of a DLL circuit.
However, a conventional phase compensation circuit explained referring to FIG. 11 has the following problems.
The first problem is that the range of the phase that can be phase compensated is limited. The reason is that this structure is such that the phase of the reference signal and the phase of the feedback signal are compensated using only one variable delay circuit.
That is, the variable delay circuit can change the delay time from the input terminal to the output terminal based on a control signal, but because the size of the variable delay circuit is finite (the number delay elements is limited), there exist a maximum value and a minimum value for the variable delay time.
Thus, for example, in the case that the phase is compensated when the delay time of the variable delay circuit is at the maximum value of the variable range, subsequently, when the delay time from the input signal to the feedback signal is increased due to a change in the operational environment, such as a fluctuation in the power source voltage or a fluctuation of the temperature, the variable delay circuit cannot further increase the delay time, and thus compensation of the phase becomes impossible.
Contrariwise, in the case that the phase is compensated when the delay time of the variable delay circuit is at the minimum value of the variable range, subsequently, when the delay time from the input signal to the feedback signal is reduced due to changes in the operating environment such as a fluctuation of the power source voltage or fluctuations of the temperature, the variable delay circuit cannot reduce delay time any further, and compensation of the phase becomes impossible.
The second problem is that when increasing the variable delay time range of the variable delay circuit with the object of increasing the range of the variable phase compensation range, the delay time of the variable delay circuit increases.
When the delay time of the variable delay circuit increases, the circuit becomes easily influenced by external influences such as power source noise, the jitter of the phase compensation circuit increases, and carrying out high precision phase compensation becomes difficult.
It is the object of the present invention to provide a phase compensation circuit that allows phase compensation grater than the variable delay time range of the variable delay circuit but does not increase more than necessary the delay time of the variable delay circuit even in the case that the phase of the reference signal and the phase of the feedback signal fluctuate due to changes in the operating environment such as the fluctuations in the power source voltage and fluctuations in temperature.
In order to attain this objective, the phase compensation circuit according to the present invention is characterized in providing a plurality of variable delay circuits whose output signal phases differ from each other by a specified cycle; a switching circuit that selects one variable delay circuit from among said plurality of variable delay circuits; a first comparator that compares the phase of the output signal of the currently selected variable delay circuit to the phase of a specified reference signal; and a control circuit that, based on the results of the comparison by said first phase comparator, controls the delay time of said currently selected variable delay circuit so that the phase of the output signal of the currently selected variable delay circuit agrees with the phase of said reference signal, and if the delay time after control exceeds the variable time delay range of the currently selected variable delay circuit, controls said switching circuit so as to select another variable delay circuit.
Preferably, the phase compensation circuit according to the present invention is characterized in further providing a second comparator that compares the phases of the outputs of said plurality of variable delay circuits to each other, and wherein said control circuit, based on the results of the comparison by said second comparison means, controls the delay time of said other variable delay circuits so that the phase of the output of the currently selected variable control circuit and the phase of the output of the other variable delay circuits differ by a specified cycle.
Preferably, two of said variable delay circuits are provided; and further said control circuit advances the phase of the output of the other variable delay circuits said specified cycle ahead the phase of the output of the currently selected variable delay circuit in the case that the delay time after said control is larger than the maximum value of the variable delay time range of the currently selected variable delay circuit, or contrariwise, delays the phase of the output of the other variable delay circuits said specified cycle behind the phase of the output of the said currently selected variable delay circuit in the case that the delay time after said control is smaller than the minimum value of the variable delay time range of the currently selected variable delay circuit.
Preferably, said specified cycle is one cycle or xc2xd cycle.
A first effect of the present invention is that even in the case that the delay time from the output signal to the feedback signal changes due to changes in the operating environment due to fluctuations in the power source voltage or fluctuations in temperature, phase compensation greater than the variable delay time range of the variable delay circuit can be carried out. The reason is that in the present invention, when the delay time of the one variable delay circuit currently selected among the plurality of variable delay circuits reaches the maximum value or minimum value of the variable time delay range, in the switching circuit the output is switched from the one variable delay circuit to another variable delay circuit whose output phase differs by one cycle from that of the one variable delay circuit, and thus phase compensation greater than the variable delay time of the variable delay circuit becomes possible.
A second effect of the present invention is that it can provide a phase compensation circuit that can carry out phase compensation without increasing more than necessary the delay time of the variable delay circuit.
A third effect of the present invention is that by making the delay time of the variable delay circuit small, jitter produced by the variable delay circuit itself can be reduced.